Why am I implementing a RISC-V softcore from scratch?

I wish I was born in the 70s, working as a software or hardware engineer on former 8-bit/16-bit systems, right before technological progress pushes later devices to be unmanageable for one human being. As far as I can tell, I always dreamed of mastering a whole computer system, from low to high abstraction levels. Computers are fascinating objects to me. Back in 2018, I started writing a basic 8-bit softcore CPU in VHDL, targeting a Nexys 3 development board, featuring a Spartan-6 Xilinx FPGA.
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