Why am I implementing a RISC-V softcore from scratch?

I wish I was born in the 70s, working as a software or hardware engineer on former 8-bit/16-bit systems, right before technological progress pushes later devices to be unmanageable for one human being. As far as I can tell, I always dreamed of mastering a whole computer system, from low to high abstraction levels. Computers are fascinating objects to me.

Back in 2018, I started writing a basic 8-bit softcore CPU in VHDL, targeting a Nexys 3 development board, featuring a Spartan-6 Xilinx FPGA. The architecture was a very limited CISC architecture designed around an accumulator register, similar to a 6502 in that regard. I wrote a rudimentary assembler in Python, feeding it an assembly file to output a binary ready to be written into the CPU instruction ROM using BRAM onto the FPGA itself. This toy project helped me to get the intuition on how data can be managed through different data paths to perform computation or flow control in a processor.

Read more →